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Double Patterning,Analog
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Introduction to Cadence Virtuoso Advanced Node Design Environment
What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing...
Posted to
Custom IC Design
(Weblog)
by
Hiro Ishikawa
on Mon, Jan 28 2013
Whitepaper: New Methodology Needed for 20nm Custom/Analog IC Design
Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no 20nm solution is complete without an integrated custom/analog capability. A newly published Cadence whitepaper...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 13 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 5 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
Free Webinars Preview 20nm Challenges, Solutions
If you're designing or planning to design at 20nm - or you're just curious about this emerging and much-discussed process node - three free webinars May 1, 2 and 3 will provide a wealth of valuable information. In these webinars, Cadence experts will team up with industry leaders to present 20nm...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 12 2012
ISQED Keynote: 20nm From a Custom/Analog Perspective
Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design ( ISQED 2012 ) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 21 2012
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