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Double Patterning,3D IC

  • TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support

    Two emerging semiconductor technologies - 16nm FinFET design and 3D-ICs - are moving closer to volume production, according to Dr. Cliff Hou, vice president for R&D at TSMC. Speaking at the TSMC Open Innovation Platform® Ecosystem Forum (TSMC OIP) Oct. 1, 2013, Hou (right) said that the EDA and...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 7 2013
  • DAC Panel: 20nm is Tough, But Not a Roadblock

    So far the move to lower semiconductor process nodes has continued unabated, but the upcoming 20nm node is causing a lot of concern. Lithography is so challenging that extra masks ( double patterning ) will be required. Will designs be technically and economically feasible? Panelists at the Design Automation...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 6 2011
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