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CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...
Posted to
Digital Implementation
(Weblog)
by
Vasu Madabushi
on Sun, Mar 10 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment
Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Tue, Jan 8 2013
Digital Logic in Analog Block – How Will You Test It?
Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 10 2012
20 Questions on 20nm – And a New Resource for Advanced Node Design
If you're currently doing or contemplating IC design at 28nm and below, you no doubt have some questions. One place to get a lot of them answered is an Advanced Node microsite newly launched by Cadence for both digital and custom/analog designers. And one interesting (and new) document you'll...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 26 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 7 2012
When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows
Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings...
Posted to
Digital Implementation
(Weblog)
by
wally1
on Thu, Apr 5 2012
Q&A: OpenAccess 10th Anniversary -- A Look Backwards and Forwards
OpenAccess is one of the most successful and impactful standards in the history of the EDA industry. By providing a C++ API, data model, and reference database implementation, OpenAccess has brought unprecedented levels of integration to analog and digital IC implementation. This year OpenAccess is celebrating...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 20 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
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