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Digital Implementation,tapeout

  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

    Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
  • Design Signoff Begins In Implementation

    As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010
  • Tapeout!

    With an early December tapeout looming, I've found myself too busy to write a post this week. But then I thought, "Why not write about tapeout?". Here are some things I try to do during a project so that those last few weeks before a deadline are as stress-free as possible: Run an early...
    Posted to Digital Implementation (Weblog) by Kari on Thu, Nov 20 2008
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