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Digital Implementation

  • How to Change a Net Name

    This is a question that comes up once every few months or so: "How do I change the name of a net that I routed by hand? Do I have to delete it and route it again?" The answer (thankfully) is no. When would you find yourself in this situation? One example is that you hand-routed a complicated...
    Posted to Digital Implementation (Weblog) by Kari on Fri, Nov 7 2008
  • Demo: Partitioning a Design in SoC-Encounter

    One of the longest standing capabilities in SoC-Encounter is its ability to partition a design- the process by which a design is broken up for hierarchical implementation. I remember seeing "Big Chip? Go Hierarchical!" in marketing material for Silicon Perspective Corporation before I joined...
    Posted to Digital Implementation (Weblog) by BobD on Thu, Nov 6 2008
  • Demo: Calling Global Timing Debug for a Single Path

    Global Timing Debug has been a very popular capability within SoC-Encounter. Once you start using it, it becomes hard to go back to looking at text reports. The high level philosophy of Global Timing Debug is to assess not just the worst path in the design- but all of the failing paths to get a feel...
    Posted to Digital Implementation (Weblog) by BobD on Fri, Oct 3 2008
  • Need for dynamic IR drop analysis at floor and power planning stages?

    Here is a question for all the power grid designers out there: Do you see the need to do quick early dynamic rail analysis during floor and power planning stages of our design? With introduction of the Cadence Encounter Power System today, Cadence First Encounter and SoC Encounter users will have access...
    Posted to Digital Implementation (Weblog) by rahuld on Mon, Sep 8 2008
  • Effectively communicating Low-Power and Power-Efficient Design knowledge

    For those of you interested in the Power space I recently had an article published on the Power Management DesignLine Europe website that talks about the challenges of capturing and communicating expertise and best practices throughout an organization (both large and small). The article talks about the...
    Posted to Digital Implementation (Weblog) by Neil Hand on Wed, Sep 3 2008
  • Demo: How To Make Multiple Edits with "Apply All" in SoC-Encounter

    Today, I'm starting what I hope will be a series of screencasts where I demonstrate some things in SoC-Encounter that I think are better shown through a live demo than through written documentation. We'll start off with a simple but somewhat hidden capability: Making edits to attributes across...
    Posted to Digital Implementation (Weblog) by BobD on Wed, Aug 27 2008
  • Who Designed the iPhone?

    When people ask you what you do for a living, is your response as clumsy as mine? "Um, you see, well I uh, work for this company that sells software that helps people design computer chips?" is typically what I say. I sometimes say "I'm an Applications Engineer for Cadence Design Systems...
    Posted to Digital Implementation (Weblog) by BobD on Wed, Jul 23 2008
  • Statistical Timing Analysis - Has its time arrived?

    At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation in semiconductor devices and interconnect has...
    Posted to Digital Implementation (Weblog) by RahulD on Mon, Jul 21 2008
  • Customer Experiences With Low-Power Design

    Hello and welcome to the new Cadence community site, and my first blog post. You will see me here from time to time posting on topics and trends in the Power Efficient Design and Low Power Design area -- and most importantly, how we as a community can play a bigger part in ensuring your success. If you...
    Posted to Digital Implementation (Weblog) by Neil Hand on Sun, Jul 13 2008
  • The Case for Robust Database Access

    The most frequently viewed forum post in the old "Digital IC->Floorplanning, Place and Route" forum initially started off as a seemingly simple inquiry: "Can CTS Stop Tracing on Hierarchical Module Ports?" From that one question came a number of suggestions and discussion...
    Posted to Digital Implementation (Weblog) by BobD on Sun, Jul 13 2008
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