Home > Community > Tags > Digital Implementation/LVS
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Digital Implementation,LVS

  • 28 nm IC Design: The Devil Is In The Details

    Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die...
    Posted to Digital Implementation (Weblog) by Nora on Mon, Mar 14 2011
  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

    Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
  • Tapeout!

    With an early December tapeout looming, I've found myself too busy to write a post this week. But then I thought, "Why not write about tapeout?". Here are some things I try to do during a project so that those last few weeks before a deadline are as stress-free as possible: Run an early...
    Posted to Digital Implementation (Weblog) by Kari on Thu, Nov 20 2008
Page 1 of 1 (3 items)