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Digital Implementation,ETS,encounter power system

  • Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
    In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012

  • Design Signoff Begins In Implementation
    As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010

  • VoltageStorm Is Alive and Kicking!
    If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, Apr 27 2009
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