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Digital Implementaion

  • Special routes with opens

    Hello everybody, I am working on floorplanning of a specific design with macro blocks (RAMs) and I have some issues : 1) My RAMs aren't connected to VDD/VSS 2) Number of Core ports routed: 0 open: 27478 Number of Followpin connections: 13739 3) When I make a verifyConnectivity, I have a message below...
    Posted to Digital Implementation (Forum) by Stewan on Wed, Jul 9 2014
  • sub threshold leakage power analysis and optimization

    Hi, Im very new to cadence. Is it possible to analyse leakage power in low digital circuits at circuit level? what is the difference between leakage power analysis at circuit level and at logic level? which tool is used to do so? I dont know how to..where to start with? My aim is to take tablet PC as...
    Posted to Digital Implementation (Forum) by amuidhay on Mon, Jul 7 2014
  • Programmable Logic Wizard Problem

    Hi everyone, I'm having a trouble creating a new project using the programmable logic wizard in OrCAD Capture. The vendor and family list is empty so I can't create a new project. How to fix this issue? Please help me as I'm fairly new to this software. Thanks.
    Posted to Digital Implementation (Forum) by ammaro90 on Sun, Apr 27 2014
  • SOC Encounter producing functionality error

    Hi all, I've ran into a particularly a troublesome error while running SOC Encounter. I'm currently implementing a design starting from behavioral verilog, synthesizing using Design Compiler and then running place and route using SOC Encounter. The problem is that the verilog netlist produced...
    Posted to Digital Implementation (Forum) by fieldy on Fri, Feb 28 2014
  • Need to trace a path from a port to all the memory_instance it is connected

    HI All, Have a query on First Encounter tool. I have a port(abc) which is connected to all the memory_pin(abc) in the design through aob's I need to trace the connectivity and dump_out the complete path through that port Second is there a way to hightlight in layout like how they are placed or view...
    Posted to Digital Implementation (Forum) by Anuragjn on Mon, Feb 3 2014
  • Re: Encounter to Virtuoso

    Hai, You can convert oa from lef using following command. 1) lef2oa -lef lef_file_name -lib output_library But std cells in the output library only in abstract view. (you can see only metals in abstract view). Also, 2) strm2oa -gds input_gds_file_name -lib output_library -techLib tech_file_name to generate...
    Posted to Digital Implementation (Forum) by selvam27 on Fri, Nov 22 2013
  • command to find the maximum and minimum drivestrength of a particular std cell

    Hai, Currently I'm writing a tcl script to fix max transition violation. In this script,I used the ecoChangeCell command to upsize and downsize the cells. I am facing a problem in this script. If I run this script, it upsize the cell upto the maximum drivestrength and after that when there is no...
    Posted to Digital Implementation (Forum) by selvam27 on Fri, Nov 22 2013
  • How to skip ERROR in cadence encounter13.2

    Hi All, When i am source eco file i am getting ERROR.so its stop due to ERROR occur. so is there any command available in encounter so we can skipp ERROR and run full file without stop anywhere?? means whenever ERROR come then it should skipp and executenext command of that eco file.
    Posted to Digital Implementation (Forum) by ajay01 on Thu, Nov 7 2013
  • set_multicycle_path regarding

    Hai friends i have doubt whether can i set a multicycle path of setup value 0 set_multicycle_path -setup 0 -from xxx -to yyyy -end will i be able to meet setup and hold for this path if setup is checked at 0 how should i give a multicycle path for a hold check Thank you
    Posted to Digital Implementation (Forum) by vimalraj on Mon, Nov 4 2013
  • Re: Writing out .lib & lef from virtuoso

    Hello Andrew, Thanks for the help.. The issue with lef is that once I export lef from virtuoso and read this to encounter,its not recognised by encounter as a macro. Can we use the lef generated by File->Export->LEF in virtuoso directly to encounter ? Or anything else need to be done for generating...
    Posted to Custom IC Design (Forum) by Shameel on Mon, Oct 7 2013
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