Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Digital Implementation forums
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Digital Implementation forums
"SoC-Encounter"
8.1
Cadence Encounter Power System
CeltIC NDC
chat
clocks
Constraint Design
CTE-TCL
dbGet
design rules
DFM
Digital Implementation
DRC
Early Rail Analysis
EDA
EDI system Encounter Digital Implementation System
encounter
Encounter Digital Implementation
Encounter Digital Implementation System 8.1
Encounter Digital Implementation System 9.1
Encounter Timing System
First Encounter
Floorplanning and Prototyping
Global Timing Debug
How To
Logic Design
low power
Low-Power
Manufacturability Sign-off
Power-Efficient Design
saveClockNets
Signoff Analysis
SoC-Encounter
SoC-Encounter 8.1
SSTA
STA
static timing analysis
testcase
verification
What you didn’t know about DFM for advanced node designs: “In-route” is insufficient
Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies. Due to the increasing...
Posted to
Digital Implementation
(Weblog)
by
mchacko
on Fri, May 14 2010
How To: Create a Self-Contained Testcase in Encounter
In the course of performing design work in Encounter, it frequently becomes desireable to create a self-contained testcase that can be shared with colleagues at other sites, or with Cadence to aid in troubleshooting tool issues. By self-contained, I mean the design data (netlist, floorplan, placement...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Thu, Jul 16 2009
Talk "Low Power" With The Experts
I am very excited about an event that Cadence low-power R&D and technical experts are hosting in Europe and eventually in other regions. The nice part about this is that it allows for informal discussions between engineers. I recently sat down with one of the presenters to find out what these events...
Posted to
Digital Implementation
(Weblog)
by
soheilm1
on Mon, Mar 9 2009
Constraint Construction: What's Its Function? Part 1 of 4
Have you found yourself frustrated at the lack of some decent timing constraints? Perhaps made critical floorplanning and placement decisions only to have them thrown out because someone forgot to mention a tiny detail in the constraints? Often times, the role of timing constraints is marginalized until...
Posted to
Digital Implementation
(Weblog)
by
Thom Moore
on Mon, Feb 9 2009
Coming This Friday January 9th: Encounter Digital Implementation Office Hours
Happy New Year everyone! I hope you all had a restful, enjoyable and healthy holiday season. I trust that you're all going through a mountain of E-mails this morning and trying to get back into the swing of working. If it helps, give yourself permission to merely get caught up on things and if you're...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Mon, Jan 5 2009
Innovate Your Way Out of Recession With the New Encounter!
It's official! The U.S. economy has been in a recession for the past year. And, the global credit crunch and economic recession has pulled the semiconductor industry down to the point of entering its eleventh recession. "I'm sorry it's happening," said US President George W. Bush...
Posted to
Digital Implementation
(Weblog)
by
RahulD
on Wed, Dec 3 2008
Coming This Friday November 14th: SoC-Encounter Office Hours
I've really been enjoying the discussions in our Digital Implementation Forums . Thanks to those who have contributed questions and answers, and to you "lurkers" out there as well. I appreciate you all- this community is nothing without you! A couple of you have reached out and sent me...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Tue, Nov 11 2008
Understanding Clock Net Markings in SoC-Encounter
I'm happy to report that the Digital Implementation Forums are picking up momentum now that the old cdnusers.org has been retired. It is great to see old friends and new ones on the new Cadence.com engaging in some really useful discussions. We had a couple of posts in particular that are frequent...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Wed, Aug 20 2008
Page 1 of 1 (8 items)