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What's Good About Single Mode Operation in DEHDL? The Secret's in the 16.5 Release!
Due to architectural changes in SPB16.5 Design Entry HDL (DEHDL), we no longer require various modes of operation -- such as Hierarchy mode, Expanded mode and Occurrence Edit mode. There will be no need to change modes while working on the schematic since the explicit need for design net listing and...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Nov 1 2011
What's Good About APD’s Die Abstract Compare? You’ll Need the 16.5 Release to See!
In the distributed co-design environment in the SPB16.5 Allegro Package Designer release, a die abstract file is used to convey die information between IC and package layout tools. For ECO purposes, it is imperative to know the changes that are incorporated inside an abstract file before incorporating...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Oct 18 2011
What's Good About Allegro GRE Disabling Bundle Compression? It’s in the 16.5 Release!
With the SPB16.5 release of Allegro Global Route Environment (GRE) , you can now prevent “Compact” routing on bundles that don’t need it. This compact routing functionality was designed to keep the delay patterns as tightly packed as possible as part of a methodology that preserved...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Oct 11 2011
What's Good About Allegro PCB Router HDI Via Tangency? Check Out 16.5!
High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI provides the ability to place components on both sides of the board and helps reduce the PCB layer stack. Allegro PCB Router started evolving in this direction from the SPB16.2 version with drill holes and microvias. In...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Wed, Oct 5 2011
What's Good About Allegro Database Locking? See for Yourself in 16.5!
Prior to the SPB16.5 release, multiple designers can edit and update the same Allegro PCB Designer design without conflict notification. To prevent this situation an advisory lock feature is now available in 16.5. Read on for more details… When opening a design for editing, Allegro PCB Designer...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Sep 27 2011
What's Good About AMS Partial Design Simulation? It’s in the 16.5 Release!
Partial Design Simulation aims at unifying the PCB and simulation flow by enabling the designer to use a single schematic for both simulation and PCB implementation. This gives the designer the ability to work with a larger design that may contain portions that will never be simulated in Allegro AMS...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Sep 20 2011
What's Good About Net Groups in Capture? Check Out the 16.5 Release and See!
A NetGroup is a collection of nets. The nets in a NetGroup can be scalar, vector or a combination of both. You can create a NetGroup that consists only of nets (like a bus). You can also create a NetGroup that consists of nets (scalar and/or vector), consists of buses, and consists of other NetGroups...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Sep 13 2011
What's Good About ADW’s Server? 16.5 Has a Few New Enhancements!
Some of the enhancements to the Allegro Design Workbench (ADW) 16.5 release were introduced in the 16.3.1 release. The 16.5 version has expanded on these with an emphasis on increased performance. The main new enhancements are: A new robust server is used Much improved server performance Lower management...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Wed, Sep 7 2011
What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!
The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as Allegro System Architect (ASA), has been enhanced to view implicit power pins in the Component Connectivity Pane (CCP). This is required for control over the power pins for the design with dies or FPGAs where an ECO is required...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Aug 30 2011
What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!
Currently, many of the SPB products support extended nets, better known as Xnets. Xnets are created automatically when a signal model is assigned to a component and that signal model defines that a connection is to be made between two pins of the component. This creates an Xnet that connects the nets...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Mon, Aug 8 2011
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