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  • Model Libraries

    I am trying to simulate a simple inverter using nmos, and pmos in Analog_Parts library but the netlist doesn't get created because of the model libraries, both of these transistors have only 3 legs, is there a .scs file to add or a different type of model libraries, where can I find such a file?
    Posted to Logic Design (Forum) by Musmar on Wed, Jun 30 2010
  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!

    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010
  • Gary Smith at DAC: SoC Design Costs Will Come Down

    System on chip (SoC) design costs are out of control and headed towards $100 million, but there's relief in sight, according to analyst Gary Smith at a Sunday presentation before the Design Automation Conference (June 14-18). In most respects Gary's speech, titled "Don't Panic! SoC Costs...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Jun 13 2010
  • Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

    The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010
  • Re: Reg .VCD file generation

    Thanks TAM1, Basically i need to calculate the power analysis in SoC Encounter. So for it i need a vcd file. Basically i have my design.v, design_testbench.v, design.sdf, .lib files, .lef files , design.sdf files that i obtained from rtl compiler. I have Model sim, xilinx and cadence encounter with...
    Posted to Logic Design (Forum) by Music on Thu, Nov 12 2009
  • User Interview: Challenges Of Analog IP Design And Verification

    Kush Gulati is CEO of Cambridge Analog Technologies , a provider of high-performance, low-power analog and mixed-signal IP. In an interview at the recent Design Automation Conference, he talked about the challenges of analog design, modeling, and simulation, and discussed some of the approaches his company...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 3 2009
  • Friday Fun: Adopting New Low-power Design Techniques

    This week's episode has the Dante Semi team employing some new low power design techniques, and using Conformal Low Power to verify their implementation of them. You will also see how the verification team uses low power simulation with Incisive to functionally verify the behavior. It's all going...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Aug 21 2009
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