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Design Entry HDL


    Hello Everyone I want to make new Schematic (cpm file) using SPB16.3 Allegro from DSN file. but i don't know how to export cpm from dsn file how can make a cpm file? thanks :)
    Posted to PCB Design (Forum) by Hi Everyone on Sun, Feb 20 2011
  • What's Good About ADW’s Library Revision Manager and Browser? Check out the ADW16.3 Release and See!

    Here are just some of the new capabilities available in the ADW16.3 Allegro Design Workbench (ADW) Library Revision Manager ( LRM ) and Component Browser ( CB ) LRM: Detects deleted parts and models Component Browser: Identifies parts removed Identifies pre-released parts Identifies parts with lifecycle...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Jan 26 2011
  • Best practices for library structures?

    I am working with our libraries right now and have an oppertunity to change them drastically if I need to. Currently, our libraries contain aproximatly 20,000 different physical parts (lines of .ptf files), about 1,000 different pad stacks, 6,500 symbols. We are creating databases for our sourcing and...
    Posted to PCB Design (Forum) by Soundman99 on Tue, Jan 4 2011
  • What's Good About Mechanical Parts in ADW? Check Out the ADW16.3 Release and See!

    Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release! There are new data model types in ADW16.3 that provide a solution for the support of mechanical models in the library and design flow. The mechanical model types supported in this release include three basic model...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Dec 1 2010
  • converting library footprints from protel to allegro

    Hi All, I have some basic doubt in converting library footprints from protel to allegro. Is it possible to convert ? Moreover am using allegro 15.2ver .In this there is no option to import protel board files. It has only import-->pads & pcad. Please help me with the procedure to do this if its...
    Posted to PCB Design (Forum) by Anonymous on Thu, Nov 25 2010
  • PSpice

    Good day! Please help me ("for dummies") with a problem! When I run PSpice, I see in *.out file(Allegro Design Entry 16.3): ERROR -- Node in is floating ERROR -- Node supply_0 is floating ERROR -- Node unnamed_1_bft92/plp_i1_e is floating ERROR -- Node diod is floating ERROR -- Node unnamed_1_bfr92a...
    Posted to PCB Design (Forum) by Tony Stark on Fri, Sep 24 2010
  • Re: Design Entry

    Tell me please! I did everything as written in User Guide. Compiled by the scheme and run it. But PSpice displays an error: ERROR -- Subcircuit ad8099 used by X_X1 is undefined What is it? The model I downloaded from the site
    Posted to PCB Design (Forum) by Tony Stark on Sun, Sep 19 2010
  • Design Entry

    Good afternoon, Comrades ! I can not write in this topic, but this kind of products Cadence discuss) Tell the Dummies : I need to simulate it two transistors: BFT 92, BFR 92. In libraries, bipolar, ebipolar, jebipolar I do not find it. In which library are discrete transistors?????? If not such elements...
    Posted to PCB Design (Forum) by Tony Stark on Fri, Sep 17 2010
  • Capture 16.3 Errors

    I'd like to report the following error in the 16.3 Version of Capture or Design Entry CIS: When converting a project from 16.01 to 16.3 Net Properties get mangled. I had a design all constrained with Propagation Delays and Relative Propagation Delays placed on a set of high-speed signal groups. When...
    Posted to PCB Design (Forum) by JWWS1 on Wed, Sep 8 2010
  • problem of plotting a Schematic in Design Entry HDL?

    when I select " Fit To Page" and use Adobe pdf printer to plot my design, the complete schematic page can not be fully displayed in one page, some of the schematic(right-bottom part) is missing, as the figure below. What's the problem? Should I change some other setting? By the way, I use...
    Posted to PCB Design (Forum) by starlin on Sat, Aug 21 2010
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