Home > Community > Tags > Design Entry HDL/16.2
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Design Entry HDL,16.2

  • omit / ignore parts in a BOM(BOM_IGNORE?), also label as "do not stuff" automatically in BOM

    I've looked at several forms/user guides/help documents and I'm unable to find the answers I'm looking for. I'm using orcad capture 16.2. I do *not* have CIS :'( 1. Is there a straightforward way to keep schematic compenonts off of the BOM. e.g. a PCB pad, fiducials, etc. EDIT: I'm...
    Posted to PCB Design (Forum) by cobcra on Tue, Dec 3 2013
  • reuse block refdes and synchronization problems

    Sorry for bothering. I encountered some problems when I work with reuse blocks. The first problem: the components inside 2 reuse blocks were assigned the same refdes, how can I change them? The second problem: the logic schematic of reuse block is not synchronized with PCB. Some signal names changed...
    Posted to PCB Design (Forum) by Samuel Zhang on Mon, Feb 21 2011
  • HDL PART TABLE FILE CHANGES

    For Part Table Files with large amount of package types (i.e. res & caps), when a value is changed or a part is added, regardless if the part is in a project, HDL is notifying and forcing the user to update their schematic when these parts are not even used in their given design. This adds a lot...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
  • LIBRARY REVISION VISIBILITY

    We currently distribute our global library over a network folder using hard coded Enviromental Veriables. The problem is that we have no way of knowing when the library was last updated. This can cause users to be un-aware of recent library updates or if they are using old revisions of the library (due...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
Page 1 of 1 (4 items)