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Debug

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 16 2013
Webinar Report: Speeding RTL and Gate-Level Simulation

Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 13 2012
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 29 2012
The Case for the Tiny Testcase

I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue they've observed on their design and I'm attempting to reproduce that behavior in a smaller...

Posted to Digital Implementation (Weblog) by BobD on Fri, Nov 16 2012
Changing the Game with Processor Based Emulation

I have always been fascinated by game changing moves. Some are more successful than others, but the general principle is always the same - coming with a gun to a knife fight. Two of my favorites are from sports. When I was a young rower, the moving outrigger was a game changer for a while and was a fascinating...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Oct 11 2012
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Aug 15 2012
SimVision Watch Window Now Accommodates Specman Watch Items

Starting from version 12.1, the SimVision Watch Window accommodates Specman watch items together with HDL watch items. Now you can use the same window to inspect all your watches. Hyperlink support in the SimVision Watch Window is still on its way, so right now Specview is the default for Specman watches...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Aug 6 2012
My Constraint was Ignored – Is it a Tool Bug? – Part 2

In a previous post we showed some cases of user code that can cause ignored constraints, and how to debug that code using the Gen Debugger. In this post, we shall demonstrate another important example -- where the user code violates IntelliGen's coding guidelines. Incorrectly written constraints...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Jul 23 2012
DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation

It is nice to see when visions get closer to reality. When Cadence announced its vision for the System Development Suite back in 2011, offering a continuum of engines from virtual prototyping through RTL simulation, acceleration and emulation all the way to FPGA based prototyping seemed aggressive. Or...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Jul 2 2012
DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currently ongoing and you can still participate here . FPGA...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Jun 28 2012

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Debug

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

Webinar Report: Speeding RTL and Gate-Level Simulation

Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

The Case for the Tiny Testcase

Changing the Game with Processor Based Emulation

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

SimVision Watch Window Now Accommodates Specman Watch Items

My Constraint was Ignored – Is it a Tool Bug? – Part 2

DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation

DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping