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DVcon

  • DVCon 2010 - Day 3

    Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3. The images and notes include highlights from: A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper The paper "Tweak Free Reuse...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 2 2010
  • DVCon Panel: Why Verification Engineers Are “Sleepless”

    I view a panel as successful when I leave the room knowing more than when I came in. Such was the case at the "What keeps you up at night" panel at DVCon Feb. 24, which offered some interesting, provocative, and in several cases surprising perspectives about challenges and solutions in IC design...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 1 2010
  • DVCon 2010 Rocked!

    I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010 , and I have to say that it was a really good show. This is arguably the most important conference of the year for verification. DAC is lots bigger of course, but DVCon is really focused and there's a core group of colleagues...
    Posted to Functional Verification (Weblog) by tomacadence on Fri, Feb 26 2010
  • DVCon 2010 - Day 2

    Click here or on the image below to go to the annotated photo blog of DVCon Day 2. Photos & notes include highlights from: Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives" Lunch panel on "OVM found the bugs, now how do we debug them faster" Cadence...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 26 2010
  • Lip-Bu Tan Keynote: Rethinking EDA For 2010 And Beyond

    Business conditions are looking up for the EDA and semiconductor industries, but customer concerns have shifted, according to Lip-Bu Tan, president and CEO of Cadence. At a DVCon keynote speech Feb. 24, Lip-Bu described a new landscape in which EDA providers must help customers be both productive and...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 25 2010
  • DVCon SystemC Day Quandry: Need for Third Party TLM IP

    Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was only a small amount of discussion about the need...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 24 2010
  • DVCon 2010 - Day 1

    Click here or on the image below to go to the photo blog of DVCon Day 1. While I've added descriptive captions to the images, allow me to address the FAQ: "How was the traffic on show floor?". My unscientific observation was that the floor was a little lighter than last year, but this was...
    Posted to Functional Verification (Weblog) by jvh3 on Wed, Feb 24 2010
  • DVCon SystemC Day – Forging A TLM Design/Verification Flow

    Advanced design technologies are of no value unless there's a coherent, workable methodology that supports them. SystemC transaction-level modeling (TLM) has lacked a methodology that goes all the way to silicon without major gaps. Independent verification consultant Brian Bailey filled in some of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 23 2010
  • DVCon "Day 0" - Quick Report From SystemC Day

    If you were looking for more evidence that the transition from RTL to ESL is gaining momentum, today at "Day 0" of DVCon (a/k/a "SystemC Day") you would discover plenty of supporting data points. Here is a brief video interview with my colleague Steve Svoboda on the day's events...
    Posted to Functional Verification (Weblog) by jvh3 on Mon, Feb 22 2010
  • DVCon: Showcasing The Cadence Passion For Verification Excellence

    Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Feb 22 2010
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