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DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups
On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “ Bringing Continuous Domain into SystemVerilog...
Posted to
Mixed-Signal Design
(Weblog)
by
PrabalB
on Fri, Mar 30 2012
Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for Analog Behavior!
In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE." Wait, aren't Property Specification Language (PSL) and SystemVerilog Assertions (SVA) digital assertion-based verification (ABV...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Mar 26 2012
Photo Essay, Video Playlist, and Comments on DVCon 2012
In addition to the annotated image gallery (click here or on the image), or the playlist of videos on some of the papers, panels, partner activities, and tutorials ((click here or on the composite image), below are some long form comments on particular aspects of this year's Design & Verification...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Mon, Mar 12 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps
In this interview Product Engineer Chris Komar recaps the tutorial on formal apps given on Thursday March 1, 2012 at DVCon. Chris outlines how the "apps" approach can tackle verification challenges that are relatively easy for formal and formal+simulation to solve, and backs this up with some...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Mar 8 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
Differentiation Through Hardware is Not Going Away
Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, Mar 5 2012
DVCon Panel: Will Differentiation Through Software Kill Chip Design?
Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 1 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?
Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 29 2012
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