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DVcon,Mixed-Signal
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Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 27 2013
DVCon 2013 Expert Panel: How to Succeed with Verification Planning
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 5 2013
Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal (UVM-MS)
E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview. It was shot during the show, but the official approval fell between the cracks and didn't come through until recently. Regardless,...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Jul 24 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups
On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “ Bringing Continuous Domain into SystemVerilog...
Posted to
Mixed-Signal Design
(Weblog)
by
PrabalB
on Fri, Mar 30 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?
Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 29 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 30 2012
Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Jan 30 2012
DVCon Wrap-Up and Blog Review
The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
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