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DVcon,DVCon 2013
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Video: A Unified Modeling Flow for Virtual Platforms and High-Level Synthesis
Can the same SystemC TLM2 models be used in virtual platforms and high-level synthesis? Today the answer is typically "no." However, there is a "middle ground" modeling methodology that can turn this "no" into a "yes," according to Stuart Swan, senior architect...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 11 2013
Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 27 2013
DVCon 2013: Functional Verification Is EDA’s “Killer App”
With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event: DVCon 2013 was a one stop...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Sun, Mar 10 2013
DVCon 2013 Expert Panel: How to Succeed with Verification Planning
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 5 2013
DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?
If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog , did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Mar 1 2013
DVCon 2013: Engineers Question EDA Standards Leaders at Accellera “Town Hall” Meeting
Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes . A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 25 2013
DVCon 2013 Lunch Panel: Best Practices in Verification Planning
While standardized methodologies guide many other aspects of functional verification, planning the verification process is as much an art as a science. How can you know if you're following "best practices" in verification planning? One way to find out is to attend a Cadence sponsored luncheon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 14 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
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