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DVFS,CPF

  • Designer View – Low-Power IC Design Challenges and Solutions

    The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 23 2012
  • GUC User Presentation at DAC: How to Do Low Power Design

    Power was clearly a hot topic at the recent Design Automation Conference (DAC). Many companies demonstrated their unique tool capabilities to address power issues at different abstraction levels. However, we saw very few presentations that offered a user perspective on how they do low power designs and...
    Posted to Low Power (Weblog) by QiWang on Mon, Jun 13 2011
  • Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together

    This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 19 2010
  • Analog Coverage Metrics in Mixed-Signal Simulations

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 5 2010
  • Error Detection for Controlled Voltage Sources and Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection. My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 21 2010
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss the simulation of closed-loop voltage scaling for adaptive dynamic voltage and frequency scaling (DVFS). My previous blogs covered some of the...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 7 2010
  • Dynamic Power Management – Closed Loop Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very...
    Posted to Low Power (Weblog) by Neyaz on Tue, Aug 24 2010
  • A Call For Power-Aware IP Models

    Power intent formats exist to express the design's low power techniques separately from the design's functional description. This promotes portability of the design across different power schemes. So why are most commercial IP providers forced to bury this critical information deep in gate-level...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Aug 3 2010
  • New Features In CPF 1.1

    This is a guest post by Qi Wang, Sr. Architect for the Cadence Low Power Solution, providing more information on what is contained in the recently-announced CPF version 1.1 . There are many major improvements in the new Si2 CPF version 1.1, and I would like to provide more details on a few of them: Complete...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 17 2009
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