Home > Community > Tags > DVCon/analog assertions/verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DVCon,analog assertions,verification

  • DVCon Wrap-Up and Blog Review

    The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 10 2011
  • DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs

    If you want to know how challenging mixed-signal verification really is, the best thing is to listen to the people in the trenches. A March 3 lunch panel at the DVCon conference, sponsored by Cadence, allowed an attentive audience to do just that. The panel included three users and two vendor representatives...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Mar 6 2011
Page 1 of 1 (2 items)