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DVCon,analog assertions,Accellera

  • DVCon Wrap-Up and Blog Review

    The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 10 2011
  • DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs

    Digital designers and verification engineers are reaping great benefits from assertion-based verification. Why should analog/mixed-signal designers be left out? A Cadence paper presented at the recent DVCon conference showed how assertions can be applied to the analog/mixed-signal world as well. The...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 10 2011
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