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DRC

  • GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

    DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 23 2011
  • Everything New is Old … Everything Old is New

    The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl) on which several classic doo-wop groups performed versions of then-current songs. It's achieved a bit of cult status since Joey Ramone contributed a song called "Doreen is Never Boring" that, as far as...
    Posted to Functional Verification (Weblog) by tomacadence on Fri, Sep 9 2011
  • What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

    Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC) markers created by Assembly Rule Checks had to be external DRC markers since no constraint IDs were associated with the ADRC constraints. In the 16.3 release, Constraint IDs were created for each of the rules. It enabled...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jul 26 2011
  • DRC License Error

    Hi, I am getting the following error when I attempt a Verify->DRC with Cadence Virtuoso 6.1.4: *WARNING* No DRC (Assura_DV_design_rule_checker) or DRC (312) license is available *WARNING* Verification program terminated Basically, I wish to use the divaDRC.rul for DRC. Please provide inputs.
    Posted to Custom IC Design (Forum) by legolas on Sun, Jul 17 2011
  • RAVEL----Custom DRC System for SiP and PCB

    "RAVEL(Relational Algebra Verification Expression Language) DRC System for SiP and PCB" have Components followed: • RAVEL DRC language – Description and exchange of design rules • RAVEL DRC engine – Checking of design rules coded in RAVEL language in SiP Layout and PCB...
    Posted to PCB Design (Forum) by AllenYang on Fri, May 27 2011
  • From Orcad Capture Schematic to PCB Layout

    Hi, Cadence: Release 16.3 OS: Windows 7 - 32-bit 1) Create the simple circuit:I connected the resistor with GND and Power only no other special IC or other component. 2) Netlist: No Error 3) DRC file: -------------------------------------------------- Checking Schematic: SCHEMATIC1 -----------------...
    Posted to PCB SKILL (Forum) by Lindaros on Tue, Mar 22 2011
  • 28 nm IC Design: The Devil Is In The Details

    Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die...
    Posted to Digital Implementation (Weblog) by Nora on Mon, Mar 14 2011
  • How Parasitic-Aware Design Flow Improves Custom/Analog Productivity

    Increasing complexity is making it harder and harder to converge on cost-effective custom/analog designs. But most attempts to radically reshape the custom IC design flow have not worked well. What's needed is a productivity aid that's conceptually easy to understand, works with existing tool...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 14 2011
  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

    Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
  • line to shape spacing error

    Hi All I have attached a doc .Please go through that doc for clarifying my doubt. I poured a dynamic copper shape for ground over the ground pin which is already connected by tracks. It shows line to shape DRC. Whether i have to add any property to that particular net alone or i have to do it in different...
    Posted to PCB Design (Forum) by Anonymous on Thu, Dec 2 2010
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