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DRC

DRC error with pcell generated by SKILL script

I've managed to program a new pcell with SKILL script. New pcell is uploaded to icfb environment by ddGetObj, and then I used separate script to generate pcell instance using dbCreateParamInst. However, when I try to run DRC, I would get "ERROR: Failure to read input file xxxx at record offset...

Posted to Custom IC SKILL (Forum) by MinYoon on Sun, Apr 29 2012
What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements!

Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional DRC checks and an enhanced DFA utility for a 4th DRC entry, and now allows backdrilling from any layer. Read on for all the details … Max Neck Length DRC Presently, the Max Neck Length constraint is applied on a...

Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Feb 28 2012
ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July . At the recent ARM TechCon...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 8 2011
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...

Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 9 2011
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...

Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 23 2011
Everything New is Old … Everything Old is New

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl) on which several classic doo-wop groups performed versions of then-current songs. It's achieved a bit of cult status since Joey Ramone contributed a song called "Doreen is Never Boring" that, as far as...

Posted to Functional Verification (Weblog) by tomacadence on Fri, Sep 9 2011
What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC) markers created by Assembly Rule Checks had to be external DRC markers since no constraint IDs were associated with the ADRC constraints. In the 16.3 release, Constraint IDs were created for each of the rules. It enabled...

Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jul 26 2011
DRC License Error

Hi, I am getting the following error when I attempt a Verify->DRC with Cadence Virtuoso 6.1.4: *WARNING* No DRC (Assura_DV_design_rule_checker) or DRC (312) license is available *WARNING* Verification program terminated Basically, I wish to use the divaDRC.rul for DRC. Please provide inputs.

Posted to Custom IC Design (Forum) by legolas on Sun, Jul 17 2011
RAVEL----Custom DRC System for SiP and PCB

"RAVEL(Relational Algebra Verification Expression Language) DRC System for SiP and PCB" have Components followed: • RAVEL DRC language – Description and exchange of design rules • RAVEL DRC engine – Checking of design rules coded in RAVEL language in SiP Layout and PCB...

Posted to PCB Design (Forum) by AllenYang on Fri, May 27 2011
From Orcad Capture Schematic to PCB Layout

Hi, Cadence: Release 16.3 OS: Windows 7 - 32-bit 1) Create the simple circuit:I connected the resistor with GND and Power only no other special IC or other component. 2) Netlist: No Error 3) DRC file: -------------------------------------------------- Checking Schematic: SCHEMATIC1 -----------------...

Posted to PCB SKILL (Forum) by Lindaros on Tue, Mar 22 2011

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DRC

DRC error with pcell generated by SKILL script

What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements!

ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

Everything New is Old … Everything Old is New

What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

DRC License Error

RAVEL----Custom DRC System for SiP and PCB

From Orcad Capture Schematic to PCB Layout