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DRC

What's Good About PCB SI Setup/Audit? 16.6 has Many New Enhancements!

The Allegro PCB SI Signal Setup and Audit commands were introduced in the 16.5 release. Enhancements have been made to these commands in the 16.6 release. Read on for more details… Selection of all Components in Component Class Setup A new top level has been added to the tree display with a label...

Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Nov 27 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 5 2012
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change

The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...

Posted to Industry Insights (Weblog) by rgoering on Fri, Nov 2 2012
Difference between checkDrc and verify geometry in EDI

Hi, Can anyone tell me what is the diff between checkDrc and verify geometry. Why we are getting too many violations while using checkDrc command. why should we use verify geometry instud of checkDrc to check the drc issues in the design

Posted to Digital Implementation (Forum) by guttapalli on Sun, Oct 14 2012
Five-Minute Tutorial: Why You Should Be Running Early DRC

Everyone knows you have to run signoff DRC before you tape out a design. Sometimes, DRC is left to exactly that moment - right before the tapeout. If major problems are found in the design at that point, the tapeout either has to be delayed, or there is a mad scramble to fix the issues. This is a situation...

Posted to Digital Implementation (Weblog) by Kari on Thu, Oct 11 2012
Inverter gpdk180 DRC error. NWELLterm NWVIA : No Stamped Connections

Hello, I`m new, studying electronics and this beginning has been though. I`ve tried to create a Inverted using gpdk180 technology, but the "NWELLterm NWVIA : No Stamped Connections" keeps popping up every time I make the layout for the PMOS. I similar problem was occurring with the NMOS part...

Posted to Custom IC Design (Forum) by althoff on Mon, Sep 10 2012
Simple Steps to Debug DRC Violations Undetected in EDI System

You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great! But when you run DRC signoff with your physical verification tool, you have violations related to the routing. What should you do...

Posted to Digital Implementation (Weblog) by wally1 on Mon, Sep 10 2012
Edit-Copy generates DRC "Line to thru pin spacing" errors

Am I missing something on how to make an array of boards? I chose Edit - Copy, provided the spacing I wanted for the boards, the number of boards to create, then clicked "All On" for the "Find" filter. I drew a box around the board, picked my origin, and then placed the new array...

Posted to PCB Design (Forum) by Icefloe on Thu, Aug 30 2012
Allegro PCB Designer : Interlayer Spacing ?

Hi, I'm currently working with Cadence 16.5 and I would like to add an interlayer spacing constraint for two adjacent layers, in order to prevent interlayer crosstalk between differential pairs. I spent some hours looking for a solution, and I found this post : http://www.cadence.com/Community/forums...

Posted to PCB Design (Forum) by mxlecanu on Thu, Jul 26 2012
User View: A 20nm Custom IC Constraint-Driven Flow

If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 25 2012

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DRC

What's Good About PCB SI Setup/Audit? 16.6 has Many New Enhancements!

Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change

Difference between checkDrc and verify geometry in EDI

Five-Minute Tutorial: Why You Should Be Running Early DRC

Inverter gpdk180 DRC error. NWELLterm NWVIA : No Stamped Connections

Simple Steps to Debug DRC Violations Undetected in EDI System

Edit-Copy generates DRC "Line to thru pin spacing" errors

Allegro PCB Designer : Interlayer Spacing ?

User View: A 20nm Custom IC Constraint-Driven Flow