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DRC,Virtuoso
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IBIS model simulation
I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
Posted to
PCB Design
(Forum)
by
niranjan madha
on Wed, Apr 17 2013
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 5 2012
User View: A 20nm Custom IC Constraint-Driven Flow
If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 25 2012
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
How Parasitic-Aware Design Flow Improves Custom/Analog Productivity
Increasing complexity is making it harder and harder to converge on cost-effective custom/analog designs. But most attempts to radically reshape the custom IC design flow have not worked well. What's needed is a productivity aid that's conceptually easy to understand, works with existing tool...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 14 2011
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Feb 23 2011
Problems Importing OA Design from Virtuoso into Encounter
Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
Posted to
Digital Implementation
(Forum)
by
TruLogic
on Mon, Jan 10 2011
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