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DRC error

  • Re: DRC errors: package to place keepout spacing

    Hello, The problem was fixed, the solution is to set the constraint of package keep out with package_height_min and not package_height_max. With constraint package_height_max, DRC will be automatically generated. Hope it can help some people.
    Posted to PCB Design (Forum) by Lowee on Wed, Jun 12 2013
  • DRC T error

    I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
    Posted to PCB Design (Forum) by tmd63 on Fri, Apr 19 2013
  • Line to Shape Spacing DRC on Every Trace

    Hello, I am just starting out with OrCAD 16.5 and I had a few questions. 1. I have imported a design from Capture but in connecting the traces I have a "Line to Shape Spacing" DRC at pretty much every 45* angle junction. It says "constraint value 5mil, actual value 0mil." It's...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 23 2012
  • Edit-Copy generates DRC "Line to thru pin spacing" errors

    Am I missing something on how to make an array of boards? I chose Edit - Copy, provided the spacing I wanted for the boards, the number of boards to create, then clicked "All On" for the "Find" filter. I drew a box around the board, picked my origin, and then placed the new array...
    Posted to PCB Design (Forum) by Icefloe on Thu, Aug 30 2012
  • Allegro PCB Designer : Interlayer Spacing ?

    Hi, I'm currently working with Cadence 16.5 and I would like to add an interlayer spacing constraint for two adjacent layers, in order to prevent interlayer crosstalk between differential pairs. I spent some hours looking for a solution, and I found this post : http://www.cadence.com/Community/forums...
    Posted to PCB Design (Forum) by mxlecanu on Thu, Jul 26 2012
  • drc flag does not show when using relative prop. delay

    drc flag does not show when using relative prop. delay. and Clines are out of spec. When sliding the net, the green/red display shows properly. It does show on nets with a min/max rule. How do I get the DRC flag to show? Thanks
    Posted to PCB Design (Forum) by Jamez on Wed, Mar 14 2012
  • DRC Error

    Hello everyone, I have a DRC error "Package to place keepin Spacing" because the component is the USB connector, so it's normal to have this DRC, and I just want to know if it's possible to allow this DRC in property edit ? Thanks you
    Posted to PCB Design (Forum) by mmoulinier on Thu, Feb 23 2012
  • Different Force and Sense Line Widths using Pin Pair Physical Constraints

    Hi all, I have been trying to find a method to specify different line widths for the same net. Specifically, I need a force line and sense line to be routed separately to single DuT pin. These lines should be different line widths since the force line carries high current and the sense line doesn't...
    Posted to PCB Design (Forum) by jackg23 on Tue, Feb 1 2011
  • Same net via to via spacing drc suppressed

    In SPB 16.3 hotfix 20 (maybe implemented in 18) Allegro Constraint manager will no longer report a same net via to via spacing drc if those vias are covered (direct connect) by a shape. Cadence says that once the via is covered with a shape the pad ceases to exist and it simply becomes a hole to hole...
    Posted to PCB Design (Forum) by Idaho Tom on Mon, Dec 6 2010
  • line to shape spacing error

    Hi All I have attached a doc .Please go through that doc for clarifying my doubt. I poured a dynamic copper shape for ground over the ground pin which is already connected by tracks. It shows line to shape DRC. Whether i have to add any property to that particular net alone or i have to do it in different...
    Posted to PCB Design (Forum) by Anonymous on Thu, Dec 2 2010
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