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DFT,test

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 22 2013
Digital Logic in Analog Block – How Will You Test It?

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 10 2012
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
Design for Test (DFT) – New Challenges at Advanced Process Nodes

Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 15 2011
How Imec and Cadence “Wrapped Up” 3D-IC Test

One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 1 2011
Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications...

Posted to Logic Design (Weblog) by Ed JM on Thu, Apr 29 2010
Logic Design and Test Design: Do they need each other?

Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...

Posted to Logic Design (Weblog) by Ed JM on Sat, Apr 17 2010
Test (and Diagnostics) ... it is now a "Value Add" Operation (how are we measuring up?)

A quote from Defect and Fault Tolerance (DFT) 2008 Symposium Key Note Speaker – Phil Nigh, IBM, PhD Carnegie Mellon University: “The role of IC testing is changing – from being viewed as mainly a non-value (cost) operation – to one which provides additional value to products....

Posted to Logic Design (Weblog) by Ed JM on Mon, Oct 13 2008

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DFT,test

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

Digital Logic in Analog Block – How Will You Test It?

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Design for Test (DFT) – New Challenges at Advanced Process Nodes

How Imec and Cadence “Wrapped Up” 3D-IC Test

Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

Logic Design and Test Design: Do they need each other?

Test (and Diagnostics) ... it is now a "Value Add" Operation (how are we measuring up?)