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DFT
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Videos, Presentations Highlight Front-End IC Design Methodologies
Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 9 2013
ISQED Keynote: How RTL Synthesis Must Change for Advanced Node Designs
Think RTL synthesis is a solved problem that needs no further discussion? Think again. In a keynote speech at the recent International Symposium on the Quality of Electronic Design ( ISQED 2013 ) Sanjiv Taneja, vice president of product engineering at the Cadence Front-End Design group, showed how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 25 2013
Whitepaper Review: Improving Gate-Level Simulation Performance
As I wrote in a January 2013 blog post , a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 18 2013
Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic
3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 22 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
difference between Random Resistance faults and deterministic faults?
what is random resistance faults? how different is it from the deterministic faults? why do we do the RRFA(random resistance fault analysis)?
Posted to
Logic Design
(Forum)
by
vipul982
on Tue, Jan 15 2013
How do I insert test point in the model?
the "analyze deterministic_faults" creates a test point insertion file in .dfa format. How do I further use this file to insert the test points in the design model?
Posted to
Logic Design
(Forum)
by
vipul982
on Tue, Jan 15 2013
test procedure in Cadence encounter test tool?
How do I write a test procedure in Cadence encounter test tool?
Posted to
Logic Design
(Forum)
by
vipul982
on Thu, Jan 10 2013
how to connect multi clock domians to only one scan chain
Hi All, I have a design which contains 3 clock domains when i tried to connect a scan chain the DFT enginr of RTL Compiler auto creat 3 different scan chanis can anyone please help me to enforce the engine to create only one chain i tried this command "connect_scan_chains -chains scan_chain0 -pack...
Posted to
Logic Design
(Forum)
by
MoKhairy
on Wed, Jan 9 2013
Does test compaction reduces tester time or memory or both?
Does test compaction reduces tester time or memory or both?
Posted to
Logic Design
(Forum)
by
vipul982
on Wed, Jan 2 2013
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