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DFM

How DRC Plus Makes DFM Easy at 28nm

Design for manufacturability (DFM) requirements have been a barrier for many design teams who are thinking about moving to lower process nodes. But can DFM actually get easier as process nodes shrink? That possibility is offered by DRC Plus (DRC+), a new technology developed by GLOBALFOUNDRIES in collaboration...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 25 2010
DAC DFM Coalition - Do You Work On Sunday Afternoons?

It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010. On the panel were: Luigi Capodieci - GLOBALFOUNDRIES...

Posted to Silicon Signoff and Verification (Weblog) by wilbur on Wed, Jul 14 2010
What you didn’t know about DFM for advanced node designs: “In-route” is insufficient

Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies. Due to the increasing...

Posted to Digital Implementation (Weblog) by mchacko on Fri, May 14 2010
Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications...

Posted to Logic Design (Weblog) by Ed JM on Thu, Apr 29 2010
Q&A: New Challenges, New Solutions In IC Implementation

Advanced nodes are raising tough new challenges for analog/mixed-signal and digital IC implementation, according to David Desharnais, group director and product manager for implementation at Cadence. In this interview, he notes where IC designers are struggling and succeeding, and describes Cadence's...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 8 2010
Top EDA Standards Efforts To Watch In 2010

There’s some good news for the New Year – it looks like 2010 will be a busy year for EDA-related standards development. Here’s a short list of significant standards efforts (alphabetical by standards body, no implied ranking) that are expected to yield some interesting results in the...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 21 2009
DFT Challenge: Evaluating The True Cost Of Test

Remember DFT? “Design For Test” faded into the background in recent years as the industry turned its focus to DFM, but if anything test is an even larger concern than it was 10 or 15 years ago. That’s because test is becoming more difficult and expensive at nanometer process nodes,...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 5 2009
Advanced Node Panel: Making The Case For Restricted Design Rules

You would think that designers would not welcome restrictions on what they do, but panelists at the recent Design Automation Conference saw restricted design rules (RDRs) as a helpful and necessary step towards 32 nm/28 nm IC design. Panelists from AMD , TSMC , Texas Instruments , and Cadence spoke Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 6 2009
DAC Report: 8 Design Managers Reveal Top Concerns

Put eight opinionated design managers from top semiconductor companies into a room, let them speak and answer questions, and some interesting perspectives will emerge. That was the case at Management Day, sponsored by Cadence, at the Design Automation Conference Tuesday, July 28. Organized by Yervant...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 29 2009
Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions...

Posted to Digital Implementation (Weblog) by mchacko on Fri, Jun 19 2009

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DFM

How DRC Plus Makes DFM Easy at 28nm

DAC DFM Coalition - Do You Work On Sunday Afternoons?

What you didn’t know about DFM for advanced node designs: “In-route” is insufficient

Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp

Q&A: New Challenges, New Solutions In IC Implementation

Top EDA Standards Efforts To Watch In 2010

DFT Challenge: Evaluating The True Cost Of Test

Advanced Node Panel: Making The Case For Restricted Design Rules

DAC Report: 8 Design Managers Reveal Top Concerns

Cadence: Committed to DFM