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ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 9 2011
Si2 Conference: New Directions for Low-Power Standards
The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 24 2011
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
Renamed Si2 Conference Updates EDA Standards
The Silicon Integration Initiative ( Si2 ) standards organization has held 15 previous OpenAccess Conferences. This year Si2 is calling their annual event, scheduled for Thursday, Oct. 20, the "Si2 Conference." In addition to OpenAccess, the one-day event will provide updates on emerging standards...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 13 2011
“In Design” DFM Signoff – the Inside Story
As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 5 2011
GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 7 2011
GTC: GLOBALFOUNDRIES Charts Course for 28nm, 20nm and Beyond
The 28nm node is "fully enabled" and ready for production ramp-up, and 20nm early adopter flows are available now, according to GLOBALFOUNDRIES executives at the Global Technology Conference (GTC) in Santa Clara, California Aug. 30. In several morning sessions, speakers updated the company's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 31 2011
DFM – Buy Tools or Hire Services? Cadence Offers Both for TSMC
If you're planning a 40nm or 28nm design with TSMC, you have two options for meeting design for manufacturability (DFM) requirements -- either buy EDA tools and run DFM checks, or turn to a services provider to run them for you. On May 9, Cadence became the first EDA partner to be certified by TSMC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 12 2011
ISQED Keynote: DFM Heads in Two New Directions
Design for manufacturability (DFM) is a fairly mature discipline that you don't hear much about these days. But a recent keynote speech outlined two interesting new developments. One new twist complements traditional model-based and rules-based approaches with pattern matching, while another brings...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 15 2011
Virtuoso IC6.1.5: Software and Fine Red Wine
Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor. Such is the case with the Virtuoso IC6.1.5 custom/analog technology release , which delivers on the promise of Silicon Realization with capabilities that maintain design...
Posted to
Custom IC Design
(Weblog)
by
NewYorkSteve
on Mon, Mar 14 2011
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