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DFM,Virtuoso

  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

    DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 23 2011
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
  • Virtuoso IC6.1.5: Software and Fine Red Wine

    Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor. Such is the case with the Virtuoso IC6.1.5 custom/analog technology release , which delivers on the promise of Silicon Realization with capabilities that maintain design...
    Posted to Custom IC Design (Weblog) by NewYorkSteve on Mon, Mar 14 2011
  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff

    Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Cadence: Committed to DFM

    On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions...
    Posted to Digital Implementation (Weblog) by mchacko on Fri, Jun 19 2009
  • EDA Industry Stays Ahead of Technology Curve

    The EDA Industry is the unsung hero behind for modern era electronic revolution since early 80s and gets the spotlight it deserves in the recent DAC newsletter . I would like to applaud the author Geoffrey James, for crediting the EDA industry in rising to the challenges associated with each and every...
    Posted to Digital Implementation (Weblog) by Nora on Tue, May 5 2009
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