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DEHDL,HDL

  • Export Physical not adding pin numbers until component is replaced in ConceptHDL

    I recently ran into a strange issue where Export Physical (with back annotation enabled) was not adding pin numbers to the component symbol in ConceptHDL. However, if I deleted the symbol from the schematc and added it back from the Component Browser, and then ran Export Physical with back annotation...
    Posted to PCB Design (Forum) by chwilso3 on Sun, Sep 8 2013
  • Design Lock in HDL / Read-only Design

    Hi, I would like to ask how to make the schematic design a read-only file. All previously created schematic designs will be uploaded in the server. These designs can be used by other design engineers for their projects. Engineers can reuse the existing designs (blocks) but are not allowed to modify or...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 11 2013
  • Updating Part (Schematic Symbol) in Design Entry HDL

    Hi, I'm using Project Manager - Design Entry HDL in creating schematic diagram. I placed a diode symbol in the schematic diagram. After awhile, the diode symbol was modified (Pack_Type was added in the properties) in the PCB Librarian - Part Developer. How can I update the diode symbol in my schematic...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 11 2013
  • Design Entry HDL Training

    Hi there! Is there any training offering for Design Entry HDL here in Philippines? Please let me know. Thanks.
    Posted to PCB Design (Forum) by comet on Thu, Jan 24 2013
  • Component Browser: Footprint is not defined for a part.

    Hi, After creating part/symbol in Part Developer using PCB Librarian, I tried to test the part in DE HDL through PCB Librarian. When I placed the part, Component Browser shows an error, Footprint is not defined for a part. What might be the cause of this error? But when I tried to export the schematic...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 19 2012
  • Design Entry CIS to Design Entry HDL

    Hi! Is it possible to convert all symbols created in CIS into HDL? How? Thanks.
    Posted to PCB Design (Forum) by maberu on Tue, Jul 10 2012
  • LIBRARY REVISION VISIBILITY

    We currently distribute our global library over a network folder using hard coded Enviromental Veriables. The problem is that we have no way of knowing when the library was last updated. This can cause users to be un-aware of recent library updates or if they are using old revisions of the library (due...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
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