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DDR4

MemCon Keynote: Why Hybrid Memory Cube Will “Revolutionize” System Memory

DDR3 and DDR4 aren't enough - it's time for a "revolution" in system memory that will offer exponential improvements in bandwidth, latency, and power efficiency, according to Scott Graham (right), general manager of Hybrid Memory Cube technology at Micron. In a keynote speech at the...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 19 2012
MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem

Do you think memory is a boring, slow-moving technology? That's definitely not the case, according to Martin Lund (right), senior vice president at Cadence and keynote speaker at the MemCon 2012 conference Sept. 18, 2012. Lund asserted that these are "exciting times" for a semiconductor...

Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 18 2012
Panel: Signal Integrity Solutions for High Data Rate Interfaces

Serial link and DDR memory interfaces are well into Gbits/second territory, making it possible to design a new generation of high-performance devices. But these new interfaces can also greatly increase signal integrity challenges. At an August 28 EDN-hosted webinar panel , experts provided a wealth of...

Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 4 2012
Video: Enabling Next-Generation DRAM with DDR4, LPDDR3, and Wide I/O

If you want low-power, high-bandwidth access to off-chip DRAM, you're going to have to do some creative design work. A recent video presentation provides a good overview of some of the challenges, and shows how more intelligent memory controller and PHY IP is needed to support next-generation standards...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 1 2012
Why Cadence Bought Sigrity – And How it May Change PCB Analysis

On July 2 Cadence announced its acquisition of Sigrity , a provider of signal integrity and power network analysis tools for PCB and IC package design. Cadence already has some technology in these areas, and many Allegro and OrCAD customers use Sigrity tools today. So why buy Sigrity, and why make this...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 12 2012
ARM TechCon Paper: Why DRAM Latency is Getting Worse

There's a general view that everything gets faster and better as technology advances, but when it comes to external memory latency, that's not the case. In a recent ARM TechCon paper Marc Greenberg, director of product marketing at Cadence, showed why DRAM latency is increasing and discussed...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 17 2011
DDR PHY Interface (DFI 3.0) Spec – Freedom of Choice for SoC Design

To implement DDR4 memory in a system-on-chip, you'll need both memory controller IP and PHY IP. If there's a standard interface between the two, you won't be locked into a particular controller/PHY combination for future designs. That's why the newly released DDR PHY Interface (DFI 3...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 19 2011
Seminar: Top 10 Essential System on Chip (SoC) Interfaces

What are the most important system on chip (SoC) interfaces that design and verification engineers need to understand? A "top ten" list presented at the August 25 Verification IP (VIP) seminar at Cadence included some old standbys and some new and emerging interface specifications. The list...

Posted to Industry Insights (Weblog) by rgoering on Sun, Aug 28 2011
New Memory Technologies, New Possibilities

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC...

Posted to Design IP (Weblog) by Neil Hand on Mon, Apr 11 2011
Memory and Storage Control – Next Frontier for Third-Party IP?

System-on-chip (SoC) design teams have learned they can be much more productive by acquiring processor and interface IP. But most teams still build their own memory and storage controllers - a task that is becoming more difficult, and returning fewer benefits, as complexity grows. Memory and storage...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 11 2011

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DDR4

MemCon Keynote: Why Hybrid Memory Cube Will “Revolutionize” System Memory

MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem

Panel: Signal Integrity Solutions for High Data Rate Interfaces

Video: Enabling Next-Generation DRAM with DDR4, LPDDR3, and Wide I/O

Why Cadence Bought Sigrity – And How it May Change PCB Analysis

ARM TechCon Paper: Why DRAM Latency is Getting Worse

DDR PHY Interface (DFI 3.0) Spec – Freedom of Choice for SoC Design

Seminar: Top 10 Essential System on Chip (SoC) Interfaces

New Memory Technologies, New Possibilities

Memory and Storage Control – Next Frontier for Third-Party IP?