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MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem
Do you think memory is a boring, slow-moving technology? That's definitely not the case, according to Martin Lund (right), senior vice president at Cadence and keynote speaker at the MemCon 2012 conference Sept. 18, 2012. Lund asserted that these are "exciting times" for a semiconductor...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Sep 18 2012
Panel: Signal Integrity Solutions for High Data Rate Interfaces
Serial link and DDR memory interfaces are well into Gbits/second territory, making it possible to design a new generation of high-performance devices. But these new interfaces can also greatly increase signal integrity challenges. At an August 28 EDN-hosted webinar panel , experts provided a wealth of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Sep 4 2012
True Stories of Assertion Driven Simulation (ADS) in the Wild
Ever since Assertion-Driven Simulation (ADS) became available, I have been working with customers to integrate ADS into their standard design and verification flow. Below are some true stories from my direct experience with ADS out in the wilds of Silicon Valley. The very first use mode I helped a customer...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Jul 5 2011
Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes”
A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with ECC and my system has the capability to use write data masks and partial-word writes. DDR3 has a reset pin, why can't I just reset it? Why do I need to initialize the memory?" The answer is "yes, you must...
Posted to
Design IP
(Weblog)
by
Marcgr
on Wed, Apr 20 2011
New Memory Technologies, New Possibilities
As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC...
Posted to
Design IP
(Weblog)
by
Neil Hand
on Mon, Apr 11 2011
Memory and Storage Control – Next Frontier for Third-Party IP?
System-on-chip (SoC) design teams have learned they can be much more productive by acquiring processor and interface IP. But most teams still build their own memory and storage controllers - a task that is becoming more difficult, and returning fewer benefits, as complexity grows. Memory and storage...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 11 2011
Q&A: Mark Gogolewski On Denali History, Acquisition, And IP Trends
Mark Gogolewski was a co-founder, CTO, and CFO of Denali Software prior to that company's recent acquisition by Cadence . He is now vice president of R&D of the Front End Group at Cadence. In this interview, he talks about Denali's history, trends in IP and memory modeling, EDA360, and the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 15 2010
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