Home > Community > Tags > DC sweep
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DC sweep

  • Re: OpAmp Simulation in Cadence Spectre

    [quote user="Andrew Beckett"] Please read the forum guidelines . You didn't really ask a question, at least not a precise question. Also, you posted on the end of a 2 year old thread, which the guidelines ask you not to do. Andrew. [/quote]
    Posted to RF Design (Forum) by ansuya on Fri, Mar 14 2014
  • Re: How to simulate DC sweep after TRAN?

    I use your first way to set up.But the results of DC sweep simulation is at the initial operating points of TRAN. And I can't drag and drop the DC analyse below the TRAN analyse in the analyses pane. DC SWEEP can't run at the final operating points of TRAN simulation. Can you give me more suggestions...
    Posted to Custom IC Design (Forum) by MOSMOS on Sun, Jul 28 2013
  • Re: Different op amp gains using different spectre analysis

    Thanks for reply, However I am facing a very strange problem in my simulation, please help me with this: I am running a parametric simulation to experiment & get the optimal bias current of Op-Amp . For this I gave a list of "I_bias" as "5u 7u " in the parametric analysis window...
    Posted to RF Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • Different op amp gains using different spectre analysis

    Hi all, I am new to analog design. I have created an op-amp schematic and tried to get open loop gain by 2 ways: (Simulation uses cadence virtuoso) 1) Transient analysis: applied a ramp pulse of 0->VDD to +ve input [with a dc value of VDD/2] and kept -ve input to Vdd/2, then plotted Vout vs V+ and...
    Posted to RF Design (Forum) by OneNewBoy on Wed, Mar 20 2013
  • transient analysis for CV plot

    Hi everyone, I want to maka a CV plot of MOSFET capacitances. By using ac analysis this is easy. The problem is that i want to keep all dc sources because they are used to bias some other controlling part of circuit. In essense I want to do transient analysis and sweep a dc source at the same time. How...
    Posted to Custom IC Design (Forum) by soathana on Wed, Oct 24 2012
  • Working with DC sweeps and OP

    Hi all, I know it's not appealing to write one's first post in an RF focused group talking about DC but please bare with me :) I am interested in plotting some MOS DC parameters like gm, gmoverid, Cgg, gds as they vary across VGS and VDS. Keeping VDS fixed for the moment, I would expect to be...
    Posted to RF Design (Forum) by MicheleA on Wed, Feb 1 2012
Page 1 of 1 (6 items)