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DATE

Is System-Level Design Creating a New Class of Engineer?

The move to electronic system level (ESL) technologies such as virtual prototyping is well underway - but what's the impact on the engineering organization? A recent panel discussion and an industry note published by analyst Gary Smith both suggested that new engineering roles are evolving, and several...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 7 2011
DATE Spotlights System Development University Investment in Europe

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's attending the University Booth at the DATE Conference in Grenoble, France March 14-18. I’m getting ready for a busy upcoming week with DATE conference in Grenoble, France. Besides organizing a workshop and...

Posted to System Design and Verification (Weblog) by Steve Brown on Thu, Mar 10 2011
Do You Have a DATE with Software? Cadence Does!

How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14-18, 2011. If you're anywhere near Grenoble in...

Posted to System Design and Verification (Weblog) by Steve Brown on Mon, Feb 28 2011
S4D Workshop: System, Software, SoC and Silicon Debug

Debugging is challenging at every step in system design - whether for hardware or embedded software, or at the System Realization, SoC Realization, or Silicon Realization levels. A day-long workshop at the upcoming Design Automation and Test (DATE) conference in Grenoble, France March 14 is taking an...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 22 2011
DAC 2010 – A “Coming Out” Party For 3D-IC Design

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the entire industry resonated with a wide gamut of system...

Posted to Digital Implementation (Weblog) by RahulD on Mon, Jun 28 2010
EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. This was my first visit and chance to rub shoulders with the industry's gurus and to discuss...

Posted to Digital Implementation (Weblog) by RahulD on Fri, Apr 16 2010
My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden, Germany, March 8th-March 12 th and offered several 3DIC topics during the conference. I heard someone say "How did 3D with TSVs become hot from cold just so quickly?" In fact it did. Last year when I was following...

Posted to Digital Implementation (Weblog) by samtabansal on Mon, Mar 29 2010
Cadence’s Andreas Kuehlmann To Head IEEE Council On EDA

With a deep involvement in conferences, publications, educational programs and awards, the IEEE Council on EDA ( CEDA ) is a behind-the-scenes organization that has a large influence on the professional EDA community. Andreas Kuehlmann, Cadence fellow and director of Cadence Research Labs , will become...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 21 2009
A Glimpse Into The Future Of High-Level Synthesis

High-level synthesis (HLS) is already in production use today, but other exciting and complementary new technologies and capabilities are coming in the future. Recently I talked with Michael “Mac” McNamara and Luciano Lavagno – both of whom are speaking at an April 24 DATE workshop...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 23 2009
A Qualcomm Perspective on 3D ICs

3D integration is a promising new technology that can potentially save space and power by stacking die in 3 dimensions. I recently spoke with Riko Radojcic, Qualcomm design lead for TSS (Through Silicon Stacking – Qualcomm’s term for 3D ICs), about how Qualcomm is deploying this technology...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 20 2009

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DATE

Is System-Level Design Creating a New Class of Engineer?

DATE Spotlights System Development University Investment in Europe

Do You Have a DATE with Software? Cadence Does!

S4D Workshop: System, Software, SoC and Silicon Debug

DAC 2010 – A “Coming Out” Party For 3D-IC Design

EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

My DATE With 3DIC Technology

Cadence’s Andreas Kuehlmann To Head IEEE Council On EDA

A Glimpse Into The Future Of High-Level Synthesis

A Qualcomm Perspective on 3D ICs