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DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional Verification
Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK , teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, Jul 5 2012
Video: Xuropa, Intel and Cadence Collaborate to Speed EDA in the Cloud
Cloud computing can generally support the types of workloads required by EDA tools, but when it comes to billion-gate semiconductor simulation, there's room for improvement. A recent collaboration between Xuropa, Intel and Cadence, presented at the user track at the June Design Automation Conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 27 2012
DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC System Verification
R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production. In this interview on the floor of the Design Automation Conference (DAC...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Jun 27 2012
Video: Easing the Design Challenges of Double Patterning at 20nm
Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Aug 23 2011
Video: Open-Silicon CEO Warns of “Exponential Verification Nightmare”
The biggest challenge with chip design and IP integration is verification, according to Naveed Sherwani, president and CEO of Open-Silicon - and things aren't getting easier. "I believe that unlike many other industries, we have not developed our verification system in a hierarchical manner...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jul 17 2011
User View: A “Structured” Approach to Managing ECOs
Engineering change orders (ECOs) are inevitable, but the need to restart chip layouts is not. Engineers at Cisco Systems' ASIC design center in Ottawa, Canada, are having good success with complex functional ECOs using a combination of manual scripts and the Cadence Encounter Conformal ECO Designer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 7 2011
Si2’s Steve Schulz: “Setting the Standards for EDA360”
EDA360 represents a significant change in which the EDA industry plays a broader role in the creation of hardware/software systems ready for applications deployment. A shift this profound must be rooted in industry standards, according to Steve Schulz, president of the Silicon Integration Initiative...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 27 2011
Video: IP Ecosystem Helps Xilinx Become a “Platform Provider”
Xilinx is making a shift from being a silicon provider to a platform provider, according to David Tokic, director of partner ecosystem alliances at Xilinx. As such, the company is increasingly relying on a broad ecosystem that includes silicon IP, EDA, and services. In a video interview at the recent...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 20 2011
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