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DAC,verification
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12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 9 2012
Video: Open-Silicon CEO Warns of “Exponential Verification Nightmare”
The biggest challenge with chip design and IP integration is verification, according to Naveed Sherwani, president and CEO of Open-Silicon - and things aren't getting easier. "I believe that unlike many other industries, we have not developed our verification system in a hierarchical manner...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jul 17 2011
Video: DAC 2011 Update From NextOp CEO Yunshan Zhu
At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp Software. After a quick update on their flagship product (BugScope 3.0), Yunshan shares his observations on how assertion synthesis can complement the Universal Verification methodology (UVM), plus he reveals specific...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, Jun 23 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API
Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Jun 22 2011
Video: Formal Verification Service Provider Oski Technology at DAC 2011
At DAC 2011, both myself and fellow Team Verify member Tom Anderson felt a distinct increase in the level of interest in Formal and assertion-based verification (ref. my DAC report , and Tom's ). We weren't the only ones: at the Oski Technology booth (the same formal verification service provider...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Wed, Jun 22 2011
DAC Panel: Users Describe Mixed-Signal Verification Challenges, Solutions
Should analog/mixed-signal verification be more like digital verification, with separate verification teams, a methodology like the Universal Verification Methodology (UVM), and metric-driven verification (MDV)? Yes, according to three mixed-signal engineers at a panel discussion at the Cadence EDA360...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 13 2011
Two New DAC Panels: 20nm Design and Mixed-Signal Verification
Two Design Automation Conference panels that you probably haven't heard off address two of the hottest issues in electronic design today. One panel focuses on 20nm design challenges, and the other tackles the perennially tough topic of mixed-signal verification. Both are free and organized by Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 31 2011
New Interview with Partner Zocalo on Their Assertion Creation Philosophy and Approach for ABV
Heads-up Team Verify subscribers: on his "Industry Insights" blog Richard Goering just interviewed Zocalo president Howard Martin about assertion-based verification methodology -- including the dangers of an ad-hoc approach to ABV. To read the interview, click here . For some additional background...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Dec 9 2010
Calypto CEO Interview: Why System Realization Needs Sequential Analysis
One important enabling technology of a transaction-level modeling (TLM) based design flow is an ability to verify the results of high-level synthesis. Calypto Design Systems , a member of the recently-formed Cadence System Realization Alliance , is playing an important role by closely integrating its...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 2 2010
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