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Designer View – Using Metric-Driven Verification for Mixed-Signal IP
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 29 2012
Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM
Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Mon, Aug 27 2012
DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional Verification
Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK , teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, Jul 5 2012
Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog
Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here . Cadence is happy to see this latest release maintaining the APIs and backward compatability of the UVM while improving the quality and stability of the SystemVerilog library. Building...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Fri, Jun 1 2012
Hot Topic: Should Separate Teams Handle Analog Verification?
Dedicated verification teams are well established in the digital world, but not in analog/mixed-signal design. Has the time come for separate analog verification teams? I've been following an ongoing debate on this topic in a couple of LinkedIn groups, a debate that followed my recent blog posting...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 21 2011
Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System Realization
My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production. In this interview on the floor of DAC...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Jun 29 2011
Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integration
One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP. Duolog is in the vanguard of creating automation to address this challenge, and in this video update Duolog's CTO Dave Murray notes new capabilities...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Sun, Jun 26 2011
Video: DAC 2011 Update From NextOp CEO Yunshan Zhu
At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp Software. After a quick update on their flagship product (BugScope 3.0), Yunshan shares his observations on how assertion synthesis can complement the Universal Verification methodology (UVM), plus he reveals specific...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, Jun 23 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API
Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Jun 22 2011
Looking Back at DAC
Last week was the 48 th Design Automation Conference (DAC), held in lovely San Diego. This was the 24 th DAC in a row I've attended, which sounds impressive although I have a number of colleagues who go back even further. This year's attendance was significantly higher than last year's by...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Wed, Jun 15 2011
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