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DAC

Digital and Analog Verification – Round Peg in a Square Hole?

Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 9 2012
2012 CES: Top 3 Trends Impacting EDA This Year

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't personally attend CES this year, I had two trusted...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Jan 17 2012
EDA “Nobel Prize” Goes to Algorithmic Pioneer

The annual Phil Kaufman award, which honors individuals who have made a significant impact on electronic design automation, is the EDA industry's equivalent of the Nobel Prize. This year's award was presented Nov. 8 at a dinner event in San Jose, California, sponsored by the EDA Consortium and...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 10 2011
Video: Easing the Design Challenges of Double Patterning at 20nm

Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video...

Posted to Industry Insights (Weblog) by rgoering on Tue, Aug 23 2011
Panel Video: Preventing IP Theft in a Global Market

How can semiconductor companies ensure IP integrity in a global marketplace? Are foundries liable if customers use stolen semiconductor IP? Do systems companies really care if their semiconductor IP is stolen? These are some of the questions that emerged at a Design Automation Conference panel in June...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 4 2011
User View: How Formal Techniques Verify Memory Wrappers

Broadcom uses a lot of memory in its video processing ICs, and that causes a simulation bottleneck, according to Normando Montecillo, senior principal engineer at Broadcom. But the company has found a better way - using formal verification and assertions to develop a new flow for verifying memory wrappers...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 27 2011
Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my experiments with social media to connect to the communities of engineers that use the products and capabilities I help bring to market. Specifically, I shared with Brian the channels I've seen work well so far, which...

Posted to Functional Verification (Weblog) by jvh3 on Thu, Jul 21 2011
Hot Topic: Should Separate Teams Handle Analog Verification?

Dedicated verification teams are well established in the digital world, but not in analog/mixed-signal design. Has the time come for separate analog verification teams? I've been following an ongoing debate on this topic in a couple of LinkedIn groups, a debate that followed my recent blog posting...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 21 2011
User View: How to Succeed With Formal Verification

If you can speed your verification by 6X while finding more bugs, that's a pretty good deal. And that's exactly what happened when Cisco Systems turned to formal verification for a complex statistics block, according to a Design Automation Conference (DAC 2011) paper authored by Oski Technology...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 20 2011
Video: Open-Silicon CEO Warns of “Exponential Verification Nightmare”

The biggest challenge with chip design and IP integration is verification, according to Naveed Sherwani, president and CEO of Open-Silicon - and things aren't getting easier. "I believe that unlike many other industries, we have not developed our verification system in a hierarchical manner...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jul 17 2011

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DAC

Digital and Analog Verification – Round Peg in a Square Hole?

2012 CES: Top 3 Trends Impacting EDA This Year

EDA “Nobel Prize” Goes to Algorithmic Pioneer

Video: Easing the Design Challenges of Double Patterning at 20nm

Panel Video: Preventing IP Theft in a Global Market

User View: How Formal Techniques Verify Memory Wrappers

Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

Hot Topic: Should Separate Teams Handle Analog Verification?

User View: How to Succeed With Formal Verification

Video: Open-Silicon CEO Warns of “Exponential Verification Nightmare”