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Cortex-A15,28nm

ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow

For several years, ARM has offered processor optimization utilities (called POPs) that help users of ARM Cortex-A series processors optimize power, performance and area for a given process. This week (Aug. 9) ARM and Cadence took things one step further by announcing a POP that includes scripts that...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 9 2012
TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 14 2012
Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 18 2011
EDA Retrospective: Ten Key Developments in 2010

Much happened in the world of EDA and electronic design in 2010, and this year-end blog post provides a quick summary of ten developments I thought were particularly notable. Some received considerable publicity, while others were hardly noticed. The list below does not include any product announcements...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 27 2010

Page 1 of 1 (4 items)

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Cortex-A15,28nm

ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

EDA Retrospective: Ten Key Developments in 2010