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Convergence,IC6.1.5

  • Problem in Cadence Virtuoso AC analysis

    Hi all, I am facing an often discussed problem while simulating a differential pair in cadence virtuoso. Though I have biased the transistors through DC (though they are in subthreshold mode), yet when I try do do ac analysis (I follow all regular steps) I get a zero magnitude at output. Ths schematic...
    Posted to Custom IC Design (Forum) by OneNewBoy on Thu, Mar 21 2013
  • High frequency quadrature VCO design with good phase noise

    Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
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