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Constraints,synthesis

  • RTL compiler command for retaining design hierarchy

    Hi, Is there a command in RTL compiler which can force the synthesizer to retain original hierarchy of the design, like there is in Xilinx ISE for instance? Thanks.
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • Propagate a clock from .LIB of a block

    Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...
    Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
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