Home > Community > Tags > Constraints/netlist files
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Constraints,netlist files

  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Regarding Xnet properties getting lost

    Hi, I am currently using 15.7 Allegro PCB Design XL. I have assigned Models to components to assign XNET properties. Whenever iam importing the latest netlist the Xnet properties are getting lost. Our schematic engineers are using Mentor Dx Designer to generate netlist in .tel format. Every time I import...
    Posted to PCB Design (Forum) by kingshar on Wed, May 26 2010
Page 1 of 1 (2 items)