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  • Regarding Models

    Hi All, I am currently using 15.7 Allegro PCB Design XL. I have assigned Models to components to assign XNET properties. Whenever I am changing the board file name is getting changed or when i am sharing the .brd filw iwth any of my collegues the Models are getting lost and thenit is throwing DRC's...
    Posted to PCB Design (Forum) by kingshar on Wed, May 26 2010
  • Constraint Manager - Diff Pair (Cadence 16.2)

    Does anyone have a good explanation on setting up constraints for diff pair to pair spacing using Allegro PCB Design XL version 16.2? I am having trouble getting the minimum line spacing set in physical constraint to override the line to line spacing set in the net class-class.
    Posted to PCB Design (Forum) by mike78 on Sat, Mar 13 2010
  • Problem with Constraints

    Hi, I was making a design into SCM and was stumped at a point. Which constraints will the board file have when I export it from SCM, if I have several components with different constraints in the design ? Is it going to consider the tightest value and use it OR is it going to carry over the values of...
    Posted to PCB Design (Forum) by Trivedi on Tue, Mar 2 2010
  • constraint file

    Hi I am new to cadence software and i would like to know How to write a constraint file for Area and Timing constraints for a simple design (AND gate)
    Posted to Logic Design (Forum) by my screen on Sat, Nov 21 2009
  • Einstein's puzzle (System Verilog) solved by Incisive92

    Hello All, Following is the einstein's puzzle solved by cadence Incisive92 (solved in less than 3 seconds -> FAST!!!!!!) Thanks, Vinay Honnavara Verification engineer at Keyu Tech vinayh@keyutech.com // Author: Vinay Honnavara // Einstein formulated this problem : he said that only 2% in the world...
  • IntelliGen Statistics Metrics Collection Utilility

    As noted in white papers, posts on the Team Specman Blog, and the Specman documentation, IntelliGen is a totally new stimulus generator than the original "Pgen" and, as a result, there is some amount of effort needed to migrate an existing verification environment to fully leverage the power...
    Posted to Functional Verification Shared Code (Forum) by Corey Goss on Thu, Jun 4 2009
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