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Constraints,Design Entry HDL,Translate

  • Capture 16.3 Errors

    I'd like to report the following error in the 16.3 Version of Capture or Design Entry CIS: When converting a project from 16.01 to 16.3 Net Properties get mangled. I had a design all constrained with Propagation Delays and Relative Propagation Delays placed on a set of high-speed signal groups. When...
    Posted to PCB Design (Forum) by JWWS1 on Wed, Sep 8 2010
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