	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Conformal

Re: LEC - gated clock latches "Unreachable"

Thanks....

Posted to Digital Implementation (Forum) by piyushoct on Mon, May 7 2012
Re: LEC - gated clock latches "Unreachable"

set flatten model -gated_clock will apply on the golden code or revised code? set flatten model -seq_constant will be applied on the golden code or revised code?

Posted to Digital Implementation (Forum) by piyushoct on Sun, May 6 2012
Why Can’t You Write My Assertions for Me? - Part 3

My last two posts have dealt with various forms of automatic assertion creation and assertion synthesis. There is little doubt that these approaches have significant value, complementing and even replacing some of the assertions written by design and verification engineers. However, I started out this...

Posted to Functional Verification (Weblog) by tomacadence on Wed, May 4 2011
Why Can’t You Write My Assertions for Me? - Part 2

In my last post , I described three different types of automatic assertions: those derived from the design, those derived from the design with some assumptions such as naming conventions, and those derived from the design plus supplemental files expressing some aspect of design intent. I finished by...

Posted to Functional Verification (Weblog) by tomacadence on Mon, Apr 25 2011
Why Can’t You Write My Assertions for Me? - Part 1

As regular readers know from previous posts , I have a lot of background in assertion-based verification (ABV) and how assertions are used in simulation and formal analysis. There has been a lot of growth in the use of both assertions and formal since I was first involved in these technologies in 1999...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Apr 5 2011
Encounter Puzzler #3 Solution: Renaming a Net Logically

Once again, the Encounter Digital Implementation designer community has stepped up to the challenge. Last week's puzzler -- renaming a net logically in Encounter -- was solved in short order. Let's add J2mh and Sims to the list of Encounter Wizards (along with regular commentator and guest blogger...

Posted to Digital Implementation (Weblog) by BobD on Wed, Mar 9 2011
The Tale of the Silicon Re-Spin and the Bug That Got Away

I'd like to continue my blog series discussing corner-case conditions of various kinds that I have encountered in my engineering career. So far they've all had happy endings. I discussed a software bug that was only in a prototype, not an actual product, so no real damage was done. I described...

Posted to Functional Verification (Weblog) by tomacadence on Thu, Feb 17 2011
Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which...

Posted to Logic Design (Weblog) by Kenneth Chang on Mon, Feb 7 2011
Advanced Mixed-Signal Designs Demand a Unified Methodology

Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced...

Posted to Mixed-Signal Design (Weblog) by nizic on Sun, Feb 6 2011
Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow

It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the semiconductor industry?" If the latter is your...

Posted to Digital Implementation (Weblog) by Design4Life on Mon, Jan 31 2011

Page 1 of 3 (26 items) 1 2 3 Next >

Popular Tags

Share

Subscribe

Contact Us

Conformal

Re: LEC - gated clock latches "Unreachable"

Re: LEC - gated clock latches "Unreachable"

Why Can’t You Write My Assertions for Me? - Part 3

Why Can’t You Write My Assertions for Me? - Part 2

Why Can’t You Write My Assertions for Me? - Part 1

Encounter Puzzler #3 Solution: Renaming a Net Logically

The Tale of the Silicon Re-Spin and the Bug That Got Away

Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

Advanced Mixed-Signal Designs Demand a Unified Methodology

Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow