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Common Power Format
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Q&A: Qi Wang Updates EDA Power Intent Format Standards
IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative ( Si2 ), or IEEE 1801 , also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 20 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP
Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 17 2012
Mixed-Signal Technology Summit in Japan Provides Technology Updates
Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Thu, Nov 29 2012
Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Mon, Sep 17 2012
Designer View – Low-Power IC Design Challenges and Solutions
The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 23 2012
Mixed Signals from European Low-Power Designers
Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Jul 25 2012
What’s Cool for Low-Power at DAC?
Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, May 30 2012
Managing Inherited Connections with CPF in Virtuoso
Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...
Posted to
Mixed-Signal Design
(Weblog)
by
AndreasLenz
on Wed, May 23 2012
Low-Power Design? Brian Bailey Gets It
Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, May 2 2012
Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Mar 7 2012
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