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ARM TechCon Paper: Early Architectural Planning With a Digital Implementation Flow
You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 30 2011
User View: How to Succeed With Formal Verification
If you can speed your verification by 6X while finding more bugs, that's a pretty good deal. And that's exactly what happened when Cisco Systems turned to formal verification for a complex statistics block, according to a Design Automation Conference (DAC 2011) paper authored by Oski Technology...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 20 2011
User View: A “Structured” Approach to Managing ECOs
Engineering change orders (ECOs) are inevitable, but the need to restart chip layouts is not. Engineers at Cisco Systems' ASIC design center in Ottawa, Canada, are having good success with complex functional ECOs using a combination of manual scripts and the Cadence Encounter Conformal ECO Designer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 7 2011
Cisco and Cadence Present Co-design Paper at DesignCon
Today at DesignCon, be sure to drop by Room 203 at 11:05 and see Cisco and Cadence present a paper that embedded.com told their newsletter subscribers will “capture the essence of the presentations at the conference and the quality of the technical solutions.” EEtimes (who now runs DesignCon...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Tue, Feb 1 2011
User Interview: When Formal Is Best For ASIC Verification
Formal verification can serve as the primary verification methodology for an entire ASIC if it meets the right criteria, according to Yogesh Bhagwat, technical lead at Cisco . At the recent CDNLive! Silicon Valley , Bhagwat described the verification of a DDR3 command buffer ASIC using the Cadence Incisive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 25 2009
CDNLive! - How To Succeed At Formal Verification
Four customer presentations at CDNLive! Silicon Valley , held Oct. 5-16, provided some valuable tips for users and prospective users of formal verification tools. The presenters included three users of Cadence Incisive Formal Verifier (IFV) and one user of the recently announced Incisive Enterprise Verifier...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 15 2009
Is Host-Code Execution History?
Before getting into the details of today's topic I'm happy to report a brand new baby girl was born on October 1 into the Andrews family of Ham Lake, MN. She is our sixth child, and the forth girl to go along with two boys. Currently, I play a lot of golf with my oldest three kids and with the...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Oct 17 2008
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