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Circuit Design,VerilogIn

  • Multi-VDD/Power-Gated Design VerilogIn

    Hi, Is there a way for the multiple-vdd and/or virtual vdd nets to be properly generated during verilogIn? The import process relies on using the schematic and symbol definitions from the artisan_cell library that is provided to us and any cells that we have power gated or supplied a lower vdd to in...
    Posted to Cadence Academic Network (Forum) by Northfork on Tue, Mar 26 2013
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