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Circuit Design
12.1
16.3
7 segment
7447A
ADE
ADE-GXL
ADE-L
ADE-XL
AMS Simulation
analog
Analog Simulation
analog/RF
analysis
APS
BCD
Bleasdale
Block-level simulation
bypass capacitor
Chip-level simulation
Circuit simulation
ConceptHDL
crystal oscillator
Cusstom IC Design
Custim IC Design
custom design technology
Custom IC Design
Electrical validation
Electromagnetic (EM)
Electromagnetic analysis
engineering
Harmonic Balance
HB
IC 6.1
ipad
ipad schematics
mixed signal
mixed-signal
mixed-signal simulators
MMSIM
MMSIM 12.1
MMSIM71
model
Modeling
MSP430
multi-vdd
optimization
Orcad
Oscillator
Parasitic analysis
PCB
PCB design
PCB Designer
PCB layout
PCB Layout and routing
PCB manufacture
PCB Service
PLL
power supply
PSpice
pspice for ipad
PSS
reuse modules
RF
RF Block Simulation
RF design
RF designer
RF Simulation
RF spectre spectreRF
RFIC
schematics capture for ipad
scripts
simulation
Simulators
SKILL
Spectre
Spectre RF
spectreRF
spice for ipad
tablet schematic design
teardrops
Test
VCO
VerilogIn
Virtuoso
Virtuoso Analog Design Environment
Virtuoso IC 6.1.3
Virtuoso Passive Component Designer
Virtuoso PCD
Virtuoso RF Designer
Virtuoso Spectre
Virtuoso Spectre Simulator GXL
Virtuoso Spectre Simulator XL
ViVA
voltage regulator
wireless integrated circuit verification
Multi-VDD/Power-Gated Design VerilogIn
Hi, Is there a way for the multiple-vdd and/or virtual vdd nets to be properly generated during verilogIn? The import process relies on using the schematic and symbol definitions from the artisan_cell library that is provided to us and any cells that we have power gated or supplied a lower vdd to in...
Posted to
Cadence Academic Network
(Forum)
by
Northfork
on Tue, Mar 26 2013
Multiple SRAMs 1 data bus
I am creating a pcb with multiple srams connected to an FPGA on 1 data bus. I intend to clock the srams and the fpga at 150 MHz. I am concerned about what issues will arise when connecting mutliple srams to the same data bus (only 1 sram will have its output enabled at a time). For example should I worry...
Posted to
PCB Design
(Forum)
by
neseroth
on Fri, Jan 25 2013
Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 2
Greetings, Simulating crystal oscillators got a lot easier in MMSIM12.1... We have made enhancements to both Harmonic Balance and transient analyses. In Part 1 , I discussed Improvements to the Harmonic Balance use model. With the new streamlined Choosing Analyses form, you now can focus on getting your...
Posted to
RF Design
(Weblog)
by
Tawna
on Thu, Dec 20 2012
Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 1
Greetings! Simulating Crystal Oscillators got a lot easier in MMSIM12.1... We have made enhancments to both Harmonic Balance and Transient analyses. In Part 1, I’ll cover Improvements to the Harmonic Balance use model. With a streamlined Choosing Analyses form you can now focus on the simulation...
Posted to
RF Design
(Weblog)
by
Tawna
on Wed, Dec 19 2012
New PCB Etch Technology. No CF4 required. Uniform results.
Plasma Etch, Inc. Eliminates Green House Gas Used In The Production of Printed Circuit Boards. Plasma Etch, Inc. of Carson City, NV has announced it has developed and is now offering the worlds first truly green plasma etching system to be used in the manufacturing production of PCB’S (printed...
Posted to
PCB Design
(Forum)
by
Plasma Etch
on Mon, Dec 10 2012
PSPICE Simulation Error "Extra Text On Line"
Hi, Working on an audio amplifier project for school and I'm trying to simulate the circuit in Pspice. When I actually go to run the simulation, I keep getting an "Extra Text On Line" error. Here's the output sim file: **** CIRCUIT DESCRIPTION **************************************...
Posted to
Cadence Academic Network
(Forum)
by
luckyleo
on Tue, Nov 27 2012
TI494 part and transformer modeling
My group and I are trying to build a transformized h-bridge dc-dc converter. I was hoping to model this on spice, but have had no luck so far. First I am trying to use an ideal transformer but do not see how you enter the turns ratio to make it step up at the right ratio. Also I was hoping to try to...
Posted to
PCB Design
(Forum)
by
Joel2012
on Mon, Nov 5 2012
not able to design 7447A 7segment IC in Pspice
I tried to design a circuit using 7447A IC the 3 connections - LT, RBI and RBO are in active low. I am not able to get valid output. What should be the inputs to these 3 connections to get a valid ouptut? I have not been able to get any help regarding this on the net. They all talk of 7447 with 16 pins...
Posted to
Cadence Academic Network
(Forum)
by
tushi
on Fri, Dec 2 2011
Spicy Schematics for iPad - great for students, engineers, and professors!
Spicy Schematics has gone through a few revisions and has some great new features! Create circuits with your fingers then save as, share with one-click via email or upload to the Spicy Schematics Online Circuit Library where others can download, and make screenshots for presentations ... use the group...
Posted to
Cadence Academic Network
(Forum)
by
EdPat
on Thu, Nov 3 2011
Voltage stays on when power is removed
Hello all, I designed a prototype circuit for my MSP430 and other components. It is powered by two voltage regulators and a current source. What confuses me is that after I remove the battery power (4.2V) from the circuit, it does not turn all the way off. V+ drops to 500mV and then drops so slowly that...
Posted to
PCB Design
(Forum)
by
jmh1022
on Tue, Oct 18 2011
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